A SiC semiconductor device achieving high breakdown electric field intensity generates a high electric field due to the high breakdown electric field intensity. In a case where the SiC semiconductor device is provided with an element of a trench gate structure, a high electric field is generated particularly at a gate bottom. Accordingly, a gate oxide film has a high electric field applied thereto and has a shorter life. In order to prevent such a shorter life, a conventional art proposes a structure in which a p-type impurity layer serving as an electric field relaxation layer is provided adjacent to a trench having a trench gate so as to relax an electric field applied to the trench gate (see Patent Literature 1). Such a structure including an electric field relaxation layer near a trench has a lower electric field applied to a gate oxide film as the electric field relaxation layer has a larger depth, so that the gate oxide film is likely to have a longer life.